The present invention relates to a semiconductor device having a buried interconnect buried in an interlayer dielectric film, and a method for fabricating the device.
In recent years, a high-integration semiconductor device such as an ultra large scale integrated circuit (ULSI) has been required to enhance the speed of signal transmission, and to be highly resistant to migration intensified by an increase in power consumption. As an interconnect material that meets such requirements, an aluminum alloy has conventionally been used. However, in order to further enhance the speed of signal transmission, low resistivity copper whose resistance to electromigration is approximately ten times as high as that of aluminum has lately been used as an interconnect material.
As processes particularly suitable for formation of copper interconnect, a single damascene process and a dual damascene process are known. A single damascene process repeats the steps of filling a connection hole, formed in an interlayer dielectric film, with a conductor material, and then removing an excess portion of the interconnect material on the interlayer dielectric film by performing chemical/mechanical polishing (hereinafter, will be called “CMP”), thus forming a plug; and forming an upper interlayer dielectric film, filling an interconnect groove, formed in the upper interlayer dielectric film, with a conductor material, and then performing CMP to form an interconnect connected to the plug. On the other hand, a dual damascene process repeats the step of: forming, in a single interlayer dielectric film, a connection hole and an interconnect groove overlapping with this connection hole, filling the connection hole and the interconnect groove with an interconnect material at the same time, and then performing CMP to remove an excess portion of the interconnect material on the interlayer dielectric film.
By using a damascene process, an interconnect can be easily formed even if copper having difficulty in being patterned by dry etching is used as an interconnect material. In particular, a dual damascene process is more advantageous than a single damascene process in that the step of filling a connection hole and an interconnect groove with an interconnect material and the subsequent CMP step are each performed only once in order to form an interconnect (see, for example, Document 1 (Japanese Unexamined Patent Publication No. 2000-299376), and Document 2 (Japanese Unexamined Patent Publication No. 2002-319617)).
FIG. 14 is a cross-sectional view illustrating the structure of a conventional semiconductor device including interconnect layers formed by performing a dual damascene process.
As shown in FIG. 14, the conventional semiconductor device includes: a substrate 110 on which semiconductor elements (not shown) such as a large number of transistors are formed; a lower interlayer dielectric film 111 provided on the substrate 110; a lower interconnect groove 113 formed in the lower interlayer dielectric film 111; a lower barrier metal layer 114 formed along a wall surface of the lower interconnect groove 113; a copper film 115 for filling the lower interconnect groove 113; an upper interlayer dielectric film 117 provided on the lower interlayer dielectric film 111; a connection hole 118 formed in the upper interlayer dielectric film 117 and an upper interconnect groove 119 formed thereon; an upper barrier metal layer 120 formed along wall surfaces of the connection hole 118 and the upper interconnect groove 119; and a copper film 121 for filling the connection hole 118 and the upper interconnect groove 119. A lower interconnect 116 is made up of the copper film 115 and the lower barrier metal layer 114, formed in the lower interlayer dielectric film 111, for filling the lower interconnect groove 113. On the other hand, the upper interconnect groove 119 is formed in an extensive region of the upper interlayer dielectric film 117 including the connection hole 118. Further, portions of the upper barrier metal layer 120 and the copper film 121 filled in the connection hole 118 constitute an upper plug 122a, while another portions of the upper barrier metal layer 120 and the copper film 121 filled in the upper interconnect groove 119 constitute an upper interconnect 122b. 